The present invention relates to a semiconductor device and method of manufacturing the same and more particularly to a Bi-MOS semiconductor device which can be used for an ECL SCRAM (emitter-coupled logic static random access memory) and the like and a manufacturing method therefor.
Recently, owing to the development of larger-scale integration of semiconductor integrated circuit devices, the formation of diffusion layers by self-alignment process has come into use so that utilizing its advantages polycrystalline silicon has been used for the gate electrodes and the wiring from electrodes in the formation for example of Bi-CMOS devices.
The following publications show examples in which a low-resistivity polycrystalline silicon layer(s) are used for the formation of the gate electrodes of MOS devices as well as the formation of the emitter and collector electrodes of a bipolar device in a Bi-MOS device.
Literature 1: Japanese Laid-Open Patent No. 55-157257 PA0 Literature 2: Japanese Laid-Open Patent No. 58-222556 PA0 Literature 3: Japanese Laid-Open Patent No. 60-38856 PA0 Literature 4: IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL. SC-21, No. 5, P. 681-P. 684, 1986; "13-ns, 500-mW, 64-Kbit ECL RAM Using HI-BICMOS Technology" PA0 Literature 5: Extended Abstracts of 18th Conference on Solid State devices and Materials, Tokyo, 1986, P. 329-322, "A 7 ns/350mW 16 Kb HI-BICMOS Static RAM".
While, in the above-mentioned literatures, the polycrystalline silicon layer is used in the formation of the gate electrodes, the wiring using a buried contact, the high resistor connected in such wiring in a CMOS device and the electrodes, particularly the emitter electrode of a bipolar transistor, as regards the polycrystalline silicon layer which is particularly related directly to the construction of the present invention, the literatures 1 and 2 disclose Bi-CMOSs of the type formed using a single-layer type polycrystalline silicon layer composed of one and the same layer. On the other hand, the literatures 3 to 5 are directed to Bi-CMOSs formed using two layers of the polycrystalline silicon layer thus disclosing their uses for ECL-SRAMs.
As will be seen from these literatures, with the Bi-CMOS, one of the devices of the CMOS, e.g., the n-MOS is used as the memory device or cell of an SRAM and n-MOS, p-MOS and bipolar devices are used as peripheral circuit devices of the SRAM. In this case, there has been no instance in which the load resistor is formed by incorporating it in at least the first-layer polycrystalline silicon when the memory device is used in the form of a cell with a high-resistive load. In other words, in the above-mentioned literatures the present situation is such that the high resistor serving as a load is formed in the second-layer wiring layer, that is, it is formed by a so-called stacked structure.
With such conventional Bi-MOS integrated circuit device, particularly in order to attain a high level of integration when using such devices as an SRAM, the main trend has been such that memory devices are composed of cells of the resistive load type instead of the full CMOS type or depletion transistor load type (n-MOS E/D type). However, presently there has been no such device incorporating a high-resistivity polycrystalline silicon layer composed of a single layer-type polycrystalline silicon layer.
Moreover, while a multi-layer structure of polycrystalline silicon is effective in accomplishing a high level of integration of the planar type, its manufacturing method involves complicated processing steps and also steps become sharp with the resulting deteriorated stepcoverage for the wiring layers, thereby giving rise to problems from wiring reliability point of view such as electromigration or stress migration. In addition, the cost is unavoidably increased by the complicated processing steps and therefore simplification of the processing steps presents a great problem.